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Chaos engineering and its application to parallel distributed processing with chaotic neural networksAIHARA, Kazuyuki.Proceedings of the IEEE. 2002, Vol 90, Num 5, pp 919-930, issn 0018-9219Article

Designing SRCOs by combining SPICE and Verilog-ATLELO-CUAUTLE, E; DUARTE-VILLASENOR, M.-A; GARCIA-ORTEGA, J.-M et al.International journal of electronics. 2007, Vol 94, Num 3-4, pp 373-379, issn 0020-7217, 7 p.Article

Geometrically-constrained, parasitic-aware synthesis of analog ICsCASTRO-LOPEZ, Rafael; FERNANDEZ, Francisco V; RODRIGUEZ VAZQUEZ, Angel et al.Proceedings of SPIE - the International Society for Optical Engineering. 2005, isbn 0-8194-5832-5, 2Vol, vol2, 673-684Conference Paper

A CMOS Low Dropout Regulator with Extended Stable Region for the Effective Series Resistance of the Output CapacitorPAN, Hsuan-I; CHEN, Chern-Lin.IEICE transactions on electronics. 2008, Vol 91, Num 8, pp 1356-1364, issn 0916-8524, 9 p.Article

International mixed-signals testing workshopKAMINSKA, Bozena; SUNTER, Stephen; MIR, Salvador et al.Microelectronics journal. 2005, Vol 36, Num 12, issn 0959-8324, 62 p.Conference Proceedings

Device mismatch and tradeoffs in the design of analog circuitsKINGET, Peter R.IEEE journal of solid-state circuits. 2005, Vol 40, Num 6, pp 1212-1224, issn 0018-9200, 13 p.Article

A 32 mW 1.25 GS/s 6b 2b/Step SAR ADC in 0.13 μm CMOSZHIHENG CAO; SHOULI YAN; YUNCHU LI et al.IEEE journal of solid-state circuits. 2009, Vol 44, Num 3, pp 862-873, issn 0018-9200, 12 p.Article

Multiscale 3D Thermal Analysis of Analog ICs: from Full-Chip to Device LevelTUROWSKI, Marek; DOOLEY, Steven; RAMAN, Ashok et al.International workshop on thermal investigation of ICs and systems. 2008, pp 64-69, isbn 978-2-35500-008-9, 1Vol, 6 p.Conference Paper

Low voltage high performance CCII for analog signal processing applicationsRAJPUT, S. S; JAMUAR, S. S.Microelectronics international. 2006, Vol 23, Num 1, pp 10-15, issn 1356-5362, 6 p.Article

On the suitability and development of layout templates for analog layout reuse and layout-aware synthesisCASTRO-LOPEZ, Rafael; FERNANDEZ, Francisco V; RODRIGUEZ VAZQUEZ, Angel et al.Proceedings of SPIE - the International Society for Optical Engineering. 2005, isbn 0-8194-5832-5, 2Vol, vol2, 661-672Conference Paper

Elaboration of gallium arsenide technology in Georgia for development of microelectronic devicesKHUCHUA, Nina P; CHAKHNAKIA, Zauri D; KHVEDELIDZE, Levan V et al.SPIE proceedings series. 2004, pp 344-353, isbn 0-8194-5324-2, 10 p.Conference Paper

Determination of non-linear harmonic distortion in SPICE using the integral function methodALEMAN, Miguel A; CERDEIRA, Antonio.International conference on microelectronics. 2004, isbn 0-7803-8166-1, 2Vol, vol 2, 593-596Conference Paper

Quantitative model for thermal behaviour of an analog integrated circuitSANDHA, Gagandeep S; SINGH, Pawan K; PRADEEP KUMAR, C et al.International Conference on Embedded Systems DesignInternational Conference on VLSI Design. 2004, pp 623-626, isbn 0-7695-2072-3, 1Vol, 4 p.Conference Paper

Symbolic noise analysis in analog integrated circuitsSANCHEZ-LOPEZ, C; TLELO-CUAUTLE, E.IEEE International Symposium on Circuits and Systems. 2004, pp 245-248, isbn 0-7803-8251-X, 4 p.Conference Paper

Memristor Applications for Programmable Analog ICsSHIN, Sangho; KIM, Kyungmin; KANG, Sung-Mo et al.IEEE transactions on nanotechnology. 2011, Vol 10, Num 2, pp 266-274, issn 1536-125X, 9 p.Article

A power efficient and simple scheme for dynamically biasing cascode amplifiers and telescopic op-ampsRAMIREZ-ANGULO, Jaime; SAWANT, Milind; LOPEZ-MARTIN, Antonio et al.Integration (Amsterdam). 2008, Vol 41, Num 4, pp 539-543, issn 0167-9260, 5 p.Article

An Externally Trimmed Integrated DC Current Regulator Insensitive to Conducted EMIREDOUTE, Jean-Michel; WALRAVENS, Cedric; VAN WINCKEL, Steven et al.IEEE transactions on electromagnetic compatibility. 2008, Vol 50, Num 1, pp 63-70, issn 0018-9375, 8 p.Article

An analytical model for hot carrier degradation in nanoscale CMOS suitable for the simulation of degradation in analog IC applicationsMARICAU, E; DE WIT, P; GIELEN, G et al.Microelectronics and reliability. 2008, Vol 48, Num 8-9, pp 1576-1580, issn 0026-2714, 5 p.Conference Paper

A complementary switched MOSFET architecture for the 1/f noise reduction in linear analog CMOS ICsKOH, Jeongwook; SCHMITT-LANDSIEDEL, Doris; THEWES, Roland et al.IEEE journal of solid-state circuits. 2007, Vol 42, Num 6, pp 1352-1361, issn 0018-9200, 10 p.Article

A CMOS chopper offset-stabilized opampWITTE, Johan F; MAKINWA, Kofi A. A; HUIJSING, Johan H et al.IEEE journal of solid-state circuits. 2007, Vol 42, Num 7, pp 1529-1535, issn 0018-9200, 7 p.Conference Paper

Two-stage placement for VLSI analogue layout designsZHANG, L; RAUT, R; JIANG, Y et al.IEE proceedings. Circuits, devices and systems. 2006, Vol 153, Num 3, pp 274-280, issn 1350-2409, 7 p.Article

High-κ Ir/TiTaO/TaN capacitors suitable for analog IC applicationsCHIANG, K. C; HUANG, C. C; CHIN, Albert et al.IEEE electron device letters. 2005, Vol 26, Num 7, pp 504-506, issn 0741-3106, 3 p.Article

Bum-in stress test of analog CMOS ICsWEY, Chin-Long; LIU, Meng-Yao.Asian test symposium. 2004, pp 360-365, isbn 0-7695-2235-1, 1Vol, 6 p.Conference Paper

A circuit design based approach for 1/f-noise reduction in linear analog CMOS IC'sKOH, Jeongwook; THEWES, Roland; SCHMITT-LANDSIEDEL, Doris et al.Symposium on VLSI Circuits. 2003, pp 222-225, isbn 0-7803-8287-0, 1Vol, 4 p.Conference Paper

Integrated chaos generatorsDELGADO-RESTITUTO, Manuel; RODRIGUEZ-VAZQUEZ, Angel.Proceedings of the IEEE. 2002, Vol 90, Num 5, pp 747-767, issn 0018-9219Article

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